1. Field of the Invention
The present invention pertains to a box for transporting semiconductor wafers. More particularly, the present invention pertains to such a box which transports the wafers in a horizontal position with shock absorbing capability in both horizontal and vertical directions.
2. Description of the Prior Art
Horizontal transport boxes for semiconductor wafers are known in the prior art. Such horizontal transport boxes are disclosed by U.S. Pat. No. 6,341,695 entitled “Containment Device for Retaining Semiconductor Wafers”, issued on Jan. 29, 2002 to Lewis. This design, while satisfactory in many respects for its intended purposes, does not include substantial shock absorbing capability. Extruded fin pins, for horizontal shock absorbing capability, have been proposed by U.S. patent application Ser. No. 10/787,489 entitled “Reduced Movement Wafer Box” filed on Feb. 25, 2004 by Forsyth. Again, this design is satisfactory in many respects. A similar design with radially pivoting latched bumpers in lieu of separate fin pins is disclosed in U.S. patent application Ser. No. 10/507,471 entitled “Wafer Box with Radially Pivoting Latch Elements” filed on Sep. 10, 2004 by Forsyth et al., wherein the latched bumpers act to contain a coin stack of wafers and protect the stack from lateral shock. Typically, foam or some similar absorbing agent is used within the top and bottom of the box to absorb vertically directed shocks. This design has been satisfactory for its intended purposes, particularly when used with semiconductor wafers with raised features on the wafer surface such as balls, caps, lenses, and optical components. However, further improvements are sought in the transportation of very thin wafers which typically have no protruding surface features and are extremely fragile.
In particular, there is a need for improvements in the transportation of stacked Fine Pitched Ball Grid Arrays (FBGA) and similar stacked chip sets. These types of assembly packaging configurations have semiconductor wafer thicknesses which approach the thickness of a sheet of paper. When shipped using prior art wafer boxes, a high percentage of these semiconductor wafers are damaged. Moreover, such wafers typically have a sharp edge profile tape that results in edge cracking and chipping, particularly if there are irregular features such as a corner edge. Such cracks or chips on the edge can migrates into the wafer core during transportation.
Additionally, there is a need for improvements in the transportation of different thicknesses and types of semiconductor wafers within a single package. For instance, it is advantageous in some circumstances to ship DRAM wafers, microprocessor wafers and DA converter wafers, thereby providing a “kit”, within a single package.